The present invention relates generally to spare gate cell circuitry and, more particularly, to configurable spare gate cells for inclusion in an integrated circuit.
Large integrated circuits such as a system-on-chip (SOC) device have many logic circuits. Often, the circuit design must be updated or changed to correct errors or bugs discovered during simulations and testing. For example, during de-bugging, last minute changes to the SOC design, sometimes called Engineering Design Orders (ECO) are made by connecting one or more spare cells already located in the design to implement the correction. A typical spare gate cell includes a collection of transistors coupled together into a pre-defined logic gate or other functional logic circuit, which can then be used to perform a certain function. These pre-defined spare gates can be configured to implement various logic functions such as NAND, NOR, inverter, etc.
One known spare gate cell includes a configurable building block circuit having at least two inputs and an output. The configurable building block circuit is capable of selectively performing a plurality of possible logic functions on signals appearing on the inputs to produce a logic signal on the output, where selection of a logic function depends on connections of the input leads of the configurable building block circuit.
The increasing pressure of time-to-market has forced IC designers to improve capability of handling incremental design changes. These design changes, known as Engineering Change Orders or ECOs, are requested after silicon chips have been manufactured, thus the photo masks need to be changed. Since it is expensive to change the photo masks, it is more efficient and less expensive if the ECO can be implemented by changing only one or more of the metal layers of the design (used for interconnect), while the base layers (for cells) remain the same.
Most current VLSI (very large scale integration) circuits are constructed with at least three metal layers and usually seven or more metal layers. Implementing changes in the metal layer is only feasible if the spare cell corresponding to the desired functionality already exists in the layout of the SOC. Thus, spare cells usually are sprinkled throughout a design. However, a further complication is that only one logic function can be performed by a spare cell at any one time so that ‘n’ spare cells are required to perform ‘n’ functionalities. Therefore, silicon area and power requirements are high.
Thus, it would be advantageous to provide a spare cell that mitigates the above disadvantages of known arrangements.